CX gate

The CX gate, the controlled-NOT or CNOT, flips the target qubit when the control qubit is $\vert 1 \rangle$ and leaves it unchanged when the control is $\vert 0 \rangle$. It acts on two qubits and takes no parameters. With the control in superposition, the two qubits come out entangled. The Circuit panel draws a dot on the control wire joined to an X box on the target wire.

Kets such as $\vert 0 \rangle$ name the basis states and rotations are described on the Bloch sphere; the qubits lesson introduces both.

Call

Matrix

The matrix uses the basis order $\vert \text{control}\;\text{target} \rangle$, that is $\vert 00 \rangle, \vert 01 \rangle, \vert 10 \rangle, \vert 11 \rangle$.

Qiskit numbers basis states with qubit 0 as the least significant bit, so Operator(CXGate()) prints the same gate in a different row and column order.

Effect on basis states

In the computational basis the control is never changed. With the control in $\vert + \rangle$ and the target in $\vert 0 \rangle$, CX produces $\tfrac{1}{\sqrt{2}}(\vert 00 \rangle + \vert 11 \rangle)$, a Bell state: measuring either qubit fixes the other.

Inverse

CX is its own inverse. Two CX gates in a row on the same control and target cancel.

Usage

The Bell pair is an H on the control followed by a CX.

from qiskit import QuantumCircuit

qc = QuantumCircuit(2, 2)
qc.h(0)
qc.cx(0, 1)
qc.measure([0, 1], [0, 1])

import { QuantumCircuit } from 'qiskit';

const circuit = QuantumCircuit(2, 2);
circuit.h(0);
circuit.cx(0, 1);
circuit.measure([0, 1], [0, 1]);

On a noiseless simulator every shot reads 00 or 11, in close to equal numbers. On hardware, noise adds some 01 and 10 counts; see Why your results look wrong.

On IonQ hardware

CX is not a native gate. IonQ's reference decomposition, equal to CX up to a global phase, uses one entangling gate with single-qubit rotations around it: RY(π/2) on the control, an XX(π/4) entangler across both qubits, RX(−π/2) on both, then RY(−π/2) on the control. The entangler is MS on Aria and ZZ on Forte, the hardware behind Qollab's QPU backends; the rotations become GPi, GPi2 and virtual Z. Each CX you write is one two-qubit native gate before IonQ's optimiser runs, and more gates means more opportunity for error. See How your circuit is compiled.

Related

• H gate
• Gate reference
• How your circuit is compiled
• Why your results look wrong